Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance IC performance, functionality, and packing density. 3D ICs can comprise multiple dies stacked one on top of another with required between-die interconnects. A known method of between-die interconnect is wiring that originates on one die, goes around the edges of the one die, and terminates on another die. 3D ICs may facilitate the integration of heterogeneous materials, devices, and signals. Before these advantages can be realized, the processes required to build ICs with multiple layers must be efficient, cost effective, compatible with current state-of-the-art silicon processing technology, and highly manufacturable, that is, provide highly reliable product with good manufacture yield. Furthermore, there are advantages to smaller dimensions of between-die interconnects, as well as closer spaced die pads and between-die interconnect. The smaller dimensions and smaller spaces provide faster circuits containing multiple die, and provide smaller, and therefore, less costly, packaging. Smaller packaging enables devices or systems comprising the smaller package to be smaller and less costly to manufacture.